High packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed for 16x16 ports switch that is targeted in Xilinx FPGA. The performance of the multi-class shared buffer switch is analysed in term of throughput and mean delay. Based on the simulation with different memory sizes, it is observed that the optimum selection of memory size under uniform traffic depends on the maximum traffic load of the switch. � 2011 IEEE.

Future network should be able to handle many types of traffic such as video conferencing, audio and data transfer. Each of this traffic has specified Quality of Service (QoS). It is crucial for the switch design to guaranteed QoS for all applications. In this paper, a new ways of handling multi-class traffic is presented. The analysis is done on N x N switch with two traffic classes, high priority for delay sensitive cells and low priority for loss sensitive cells. To avoid starvation problem in low priority class, a novel approach have been introduced in the scheduling technique. By applying dual threshold setting, a better control on priority setting for both classes can be achieved. The threshold value is set based on the waiting time and threshold serving probability value. The proposed method has been simulated to show that the starvation problem can be overcome.