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Task mapping and routing optimization for hard real-time Networks-on-Chip

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dc.FundingDetailsUniversiti Sains Islam Malaysia,�USIM: PPP/USG-0116/ISI/FKAB/30/12616
dc.FundingDetailsThe authors are grateful to the Universiti Sains Islam Malaysia (USIM) for providing support for this research work under grant PPP/USG-0116/ISI/FKAB/30/12616.
dc.contributor.affiliationsFaculty of Science and Technology
dc.contributor.affiliationsFaculty of Engineering and Built Environment
dc.contributor.affiliationsUniversiti Sains Islam Malaysia (USIM)
dc.contributor.affiliationsINTI International University
dc.contributor.authorSayuti M.N.S.M.en_US
dc.contributor.authorRidzuan F.H.M.en_US
dc.contributor.authorAbdullah Z.H.en_US
dc.date.accessioned2024-05-29T02:02:09Z
dc.date.available2024-05-29T02:02:09Z
dc.date.issued2019
dc.descriptionBulletin of Electrical Engineering and Informatics Vol.8, No.2, June2019, pp. 414~421 ISSN: 2302-9285, DOI: 10.11591/eei.v8i2.1395en_US
dc.description.abstractInterference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system's schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.en_US
dc.description.natureFinalen_US
dc.identifier.doi10.11591/eei.v8i2.1395
dc.identifier.doihttps://doi.org/10.11591/eei.v8i2.1395
dc.identifier.epage421
dc.identifier.issn20893191
dc.identifier.issue2
dc.identifier.scopus2-s2.0-85071379340
dc.identifier.spage414
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85071379340&doi=10.11591%2feei.v8i2.1395&partnerID=40&md5=d1ceec79a4da6d71b57007035d73824b
dc.identifier.urihttps://beei.org/index.php/EEI/article/view/1395
dc.identifier.urihttps://oarep.usim.edu.my/handle/123456789/10202
dc.identifier.volume8
dc.languageEnglish
dc.language.isoen_USen_US
dc.publisherInstitute of Advanced Engineering and Scienceen_US
dc.relation.ispartofBulletin of Electrical Engineering and Informaticsen_US
dc.sourceScopus
dc.subjectDesign space explorationen_US
dc.subjectNetwork routingen_US
dc.subjectNetworks-on-Chipen_US
dc.subjectReal-time systemsen_US
dc.subjectSchedulabilityen_US
dc.subjectTask mappingen_US
dc.titleTask mapping and routing optimization for hard real-time Networks-on-Chipen_US
dc.typeArticleen_US
dspace.entity.typePublication

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