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Implementation of multi-class shared buffer with finite memory size

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dc.Conferencecode88886
dc.Conferencedate2 October 2011 through 5 October 2011
dc.ConferencelocationKota Kinabalu, Sabah
dc.Conferencename17th Asia Pacific Conference on Communications, APCC 2011
dc.contributor.affiliationsFaculty of Science and Technology
dc.contributor.affiliationsTelekom Research and Development
dc.contributor.affiliationsUniversiti Sains Islam Malaysia (USIM)
dc.contributor.affiliationsUniversiti Putra Malaysia (UPM)
dc.contributor.authorRahman A.A.A.en_US
dc.contributor.authorSeman K.en_US
dc.contributor.authorSaadan K.en_US
dc.contributor.authorAzman A.en_US
dc.date.accessioned2024-05-28T08:32:36Z
dc.date.available2024-05-28T08:32:36Z
dc.date.issued2011
dc.description.abstractHigh packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed for 16x16 ports switch that is targeted in Xilinx FPGA. The performance of the multi-class shared buffer switch is analysed in term of throughput and mean delay. Based on the simulation with different memory sizes, it is observed that the optimum selection of memory size under uniform traffic depends on the maximum traffic load of the switch. � 2011 IEEE.en_US
dc.description.natureFinalen_US
dc.description.sponsorshipIEEE Communication Society Malaysia Chapteren_US
dc.description.sponsorshipVTS Malaysiaen_US
dc.description.sponsorshipIEEEen_US
dc.identifier.ArtNo6152869
dc.identifier.doi10.1109/APCC.2011.6152869
dc.identifier.epage552
dc.identifier.isbn9781460000000
dc.identifier.scopus2-s2.0-84857807732
dc.identifier.spage548
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84857807732&doi=10.1109%2fAPCC.2011.6152869&partnerID=40&md5=76e53fb94a2699f60a67f1fbf2e0252a
dc.identifier.urihttps://oarep.usim.edu.my/handle/123456789/9028
dc.languageEnglish
dc.language.isoen_USen_US
dc.relation.ispartof17th Asia-Pacific Conference on Communications, APCC 2011en_US
dc.sourceScopus
dc.subjectarchitecture designen_US
dc.subjectfinite memory sizeen_US
dc.subjectFPGAen_US
dc.subjectmulti-classen_US
dc.subjectShared bufferen_US
dc.titleImplementation of multi-class shared buffer with finite memory sizeen_US
dspace.entity.typePublication

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