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Cell drop threshold architecture for multi-class shared buffer with finite memory size

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dc.Conferencecode89113
dc.Conferencedate4 December 2011 through 7 December 2011
dc.ConferencelocationPenang
dc.Conferencename2011 IEEE Conference on Computer Applications and Industrial Electronics, ICCAIE 2011
dc.contributor.affiliationsFaculty of Science and Technology
dc.contributor.affiliationsTelekom Research and Development
dc.contributor.affiliationsUniversiti Sains Islam Malaysia (USIM)
dc.contributor.affiliationsUniversiti Putra Malaysia (UPM)
dc.contributor.authorAbdul Rahman A.A.en_US
dc.contributor.authorSeman K.en_US
dc.contributor.authorSaadan K.en_US
dc.contributor.authorSamingan A.K.en_US
dc.contributor.authorAzman A.en_US
dc.date.accessioned2024-05-28T08:30:32Z
dc.date.available2024-05-28T08:30:32Z
dc.date.issued2011
dc.description.abstractShared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this paper, we analyse the performance of shared buffer with different threshold settings. The multi-class shared buffer architecture is developed for 16x16 ports switch, which is targeted for Xilinx FPGA implementation. The performance of the multi-class shared buffer switch is analysed in term of the achievable throughput as well as the drop probability. Based on the simulation with different threshold settings, it is observed that the optimum selection of cell drop threshold depends on the size of the shared buffer that triggers the RAM threshold. � 2011 IEEE.
dc.description.natureFinalen_US
dc.description.sponsorshipIEEE Malaysia
dc.description.sponsorshipIEEE Malaysia Power Electron. (PEL)/
dc.description.sponsorshipInd. Electron. (IE)/Ind. Appl. (IA) Jt. Chapter
dc.description.sponsorshipIEEE Engineering in Medicine and
dc.description.sponsorshipBiology Malaysia Chapter
dc.identifier.ArtNo6162153
dc.identifier.doi10.1109/ICCAIE.2011.6162153
dc.identifier.epage324
dc.identifier.isbn9781460000000
dc.identifier.scopus2-s2.0-84858782348
dc.identifier.spage319
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84858782348&doi=10.1109%2fICCAIE.2011.6162153&partnerID=40&md5=1ad450b62b3b394abf3aa8b27a90af56
dc.identifier.urihttps://oarep.usim.edu.my/handle/123456789/8951
dc.languageEnglish
dc.language.isoen_US
dc.relation.ispartofICCAIE 2011 - 2011 IEEE Conference on Computer Applications and Industrial Electronics
dc.sourceScopus
dc.subjectarchitecture designen_US
dc.subjectcell drop thresholden_US
dc.subjectmulti-classen_US
dc.subjectShared bufferen_US
dc.subjectArchitecture designsen_US
dc.subjectDrop probabilityen_US
dc.subjectFinite memoryen_US
dc.subjectHigh classen_US
dc.subjectLow classen_US
dc.subjectMulti-classen_US
dc.subjectOptimum selectionen_US
dc.subjectShared bufferen_US
dc.subjectShared buffer switchen_US
dc.subjectThreshold settingen_US
dc.subjectXilinx FPGAen_US
dc.subjectComputer applicationsen_US
dc.subjectCytologyen_US
dc.subjectDropsen_US
dc.subjectIndustrial electronicsen_US
dc.subjectMemory architectureen_US
dc.titleCell drop threshold architecture for multi-class shared buffer with finite memory size
dc.typeConference Paperen_US
dspace.entity.typePublication

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