Hardware Implementation Of Modified A5/1 Stream Cipher

This paper describes the implementation of the modified cryptographic algorithm namely A5/1 stream cipher which is widely used in Global System for Mobile (GSM) communication. While there are numerous published work on the A5/1 stream, very few have implemented the modified design into hardware and none of them, to the best of the author’s knowledge, has clearly analyzed as to how the different characteristics of the conventional A5/1 stream cipher would affect performance at hardware level implementation. Two modified designs with different total bits and combinational functions are implemented into hardware by means of an Field Programmable Gate Array (FPGA) board and the throughput, area consumption, power consumption as well as the throughput-to-area ratio performance of the hardware are analysed and compared with that of the conventional design of the A5/1 stream cipher. While the algorithms in use have the same level of randomness, and hence strength in terms of security, at the hardware level, when total bits in use is increased, the total power consumed actually reduces. It is also observed that the use of the XOR logic has the better power consumption rate, compared to when a multiplexer is implemented as the combinational function.

Index Terms—A5/1 stream cipher, field programmable gate array, FPGA, throughput, cryptographic algorithm.