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Implementation of Multi-Class Shared Buffer with Finite Memory Size

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dc.ConferencecodeMICC, IEEE Commun Soc, Malaysia Chapter, VTS, IEEE, China Inst Commun (CIC), Korea Informat & Commun Soc (KICS), IEICE Commun Soc
dc.ConferencedateOCT 02-05, 2011
dc.ConferencelocationKota Kinabalu, MALAYSIA
dc.Conferencename17th Asia-Pacific Conference on Communications (APCC)
dc.contributor.authorRahman, AAAen_US
dc.contributor.authorSeman, Ken_US
dc.contributor.authorSaadan, Ken_US
dc.contributor.authorAzman, Aen_US
dc.date.accessioned2024-05-29T02:50:42Z
dc.date.available2024-05-29T02:50:42Z
dc.date.issued2011
dc.description.abstractHigh packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed for 16x16 ports switch that is targeted in Xilinx FPGA. The performance of the multi-class shared buffer switch is analysed in term of throughput and mean delay. Based on the simulation with different memory sizes, it is observed that the optimum selection of memory size under uniform traffic depends on the maximum traffic load of the switch.
dc.identifier.epage552
dc.identifier.issn2163-0771
dc.identifier.scopusWOS:000320370200103
dc.identifier.spage548
dc.identifier.urihttps://oarep.usim.edu.my/handle/123456789/11101
dc.languageEnglish
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.relation.ispartof17th Asia-Pacific Conference On Communications (Apcc 2011)
dc.sourceWeb Of Science (ISI)
dc.subjectShared bufferen_US
dc.subjectmulti-classen_US
dc.subjectfinite memory sizeen_US
dc.subjectarchitecture designen_US
dc.subjectFPGAen_US
dc.titleImplementation of Multi-Class Shared Buffer with Finite Memory Sizeen_US
dspace.entity.typePublication

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