Rahman A.A.A.Seman K.Saadan K.Azman A.2024-05-282024-05-282011978146000000010.1109/APCC.2011.61528692-s2.0-84857807732https://www.scopus.com/inward/record.uri?eid=2-s2.0-84857807732&doi=10.1109%2fAPCC.2011.6152869&partnerID=40&md5=76e53fb94a2699f60a67f1fbf2e0252ahttps://oarep.usim.edu.my/handle/123456789/9028High packet network have become an essential in modern multimedia communication. Shared buffer is commonly used to utilize the buffer in the switch. In this paper, we analyse the performance of shared buffer with different memory sizes. The architecture of the multi-class shared buffer is developed for 16x16 ports switch that is targeted in Xilinx FPGA. The performance of the multi-class shared buffer switch is analysed in term of throughput and mean delay. Based on the simulation with different memory sizes, it is observed that the optimum selection of memory size under uniform traffic depends on the maximum traffic load of the switch. � 2011 IEEE.en-USarchitecture designfinite memory sizeFPGAmulti-classShared buffer5485526152869