Abdul Rahman A.A.Seman K.Saadan K.Samingan A.K.Azman A.2024-05-282024-05-282011978146000000010.1109/ICCAIE.2011.61621532-s2.0-84858782348https://www.scopus.com/inward/record.uri?eid=2-s2.0-84858782348&doi=10.1109%2fICCAIE.2011.6162153&partnerID=40&md5=1ad450b62b3b394abf3aa8b27a90af56https://oarep.usim.edu.my/handle/123456789/8951Shared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this paper, we analyse the performance of shared buffer with different threshold settings. The multi-class shared buffer architecture is developed for 16x16 ports switch, which is targeted for Xilinx FPGA implementation. The performance of the multi-class shared buffer switch is analysed in term of the achievable throughput as well as the drop probability. Based on the simulation with different threshold settings, it is observed that the optimum selection of cell drop threshold depends on the size of the shared buffer that triggers the RAM threshold. � 2011 IEEE.en-USarchitecture designcell drop thresholdmulti-classShared bufferArchitecture designsDrop probabilityFinite memoryHigh classLow classMulti-classOptimum selectionShared bufferShared buffer switchThreshold settingXilinx FPGAComputer applicationsCytologyDropsIndustrial electronicsMemory architectureRandom access storageCellsConference Paper3193246162153