This paper describes the implementation of the modified cryptographic algorithm namely A5/1 stream cipher which is widely used in Global System for Mobile (GSM) communication. While there are numerous published work on the A5/1 stream, very few have implemented the modified design into hardware and none of them, to the best of the author’s knowledge, has clearly analyzed as to how the different characteristics of the conventional A5/1 stream cipher would affect performance at hardware level implementation. Two modified designs with different total bits and combinational functions are implemented into hardware by means of an Field Programmable Gate Array (FPGA) board and the throughput, area consumption, power consumption as well as the throughput-to-area ratio performance of the hardware are analysed and compared with that of the conventional design of the A5/1 stream cipher. While the algorithms in use have the same level of randomness, and hence strength in terms of security, at the hardware level, when total bits in use is increased, the total power consumed actually reduces. It is also observed that the use of the XOR logic has the better power consumption rate, compared to when a multiplexer is implemented as the combinational function. Index Terms—A5/1 stream cipher, field programmable gate array, FPGA, throughput, cryptographic algorithm.

Background: A5/1 is well-known as the encryption standard for GSM communication, one of the most largely used cellular system in the world. Despite the popularity, its credibility was severed when its design was leaked in 1999 which consequently posed a threat to user’s privacy and confidentiality. The disclosure, incidentally, unveiled some weaknesses of the A5/1 stream cipher design such as short register phase, collision problem and simple combinational function. In this paper, a modified A5/1 is described. The proposed design looked at the effect of altering the combinational function from that of XOR to one using a 4-to-1 multiplexer (Mux) to increase the complexity of the algorithm which in turn will enhance its random features, and thus making it more secure overall. The generated output from the proposed design will be tested using the National Institute of Standard and Technology (NIST) test suite. The result will then be compared with that obtained using the modified design by Zakaria et. al. (2014), and next, analyzed. Objective: The objective for this study is to analyze and compare the use of different parameter toward the randomness of modified A5/1 structure by using the NIST test suite. Results: The analysis computed by the NIST test suite shows that the author’s proposed version is more secure compared to that of Zakaria et. al.’s version. Conclusion: The author’s version is shown to be more secure compared to that of Zakaria et. al. (2011), and while its randomness is comparable to that of the original A5/1 version, its structure is not that of public’s knowledge and will therefore minimize its probability of being deciphered.

The need of a long battery life span is crucial in portable devices. Following that, this study is conducted to extensively monitor the current performance drawn from the Arduino Nano and ST Arm Core ST32L152RE used as the controller in a portable dialysis system, specifically at the Active and Low Power Mode. The results obtained showed that the ST Arm Core ST32L152RE managed to achieve 99.99% current saving as opposed to the Arduino which gave a rate of 99.74%, despite the fact that the former runs at twice the frequency of the latter. � 2018 IEEE.